Hardware functional verification systems (“emulators”) are programmable devices used to verify hardware designs and integrated circuits having very high logic densities, and large numbers of logic gates. A common method of design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit of the hardware. These processor-based emulators sequentially evaluate combinatorial logic levels in the design under verification, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware. The complexity and number of logic gates present on an integrated circuit increases significantly every year. In order to emulate such large, high-gate-count, integrated circuits, processor-based hardware emulators now commonly contain dozens or hundreds of logic emulation chips, each emulation chip containing hundreds or thousands of processors. The term “emulation chip” is used broadly to include both monolithic integrated circuits as well as multi-chip packages. These emulation chips themselves are generally ASICs, designed or configured specifically for emulation.
As emulation systems continue to grow in size and complexity, the bandwidth requirements of the controlling interface connected to a host workstation grow as well. Controlling software running on the host workstation manages emulator resources and various user processes accessing those resources. Program access to configure and control the emulation chips is achieved through the use of many control registers in the emulation chips. The various bit positions in those registers determine the state, function, configuration, and operation of parts of the emulation chip, the whole emulation chip, or the entire system. An emulation chip may have as many as four thousand ninety-six, each having sixteen control registers, for a total of sixty-four thousand control registers per emulation chip. Since there may be dozens or hundreds of emulation chips, the number of control registers can be more than a million. As bandwidth requirements of the communication channels to the emulation chips increase, the general size of transfers across the channels also increases.
One common method for changing individual bits in a register is to read the register to determine its present state, and write an updated value back to the register, changing only the desired bits while leaving other bits in their previous state. On a communication channel with high-latency, this read-modify-write method of register access requires significant time on the communications channel, using already scarce communication channel resources.
Another common method for changing individual bits in a register involves keeping shadow copy of the registers in the local memory on the host workstation, for instance in RAM. As the central software of the host workstation updates registers via the communication channel, it also updates its local shadow copy. This eliminates some of the multiple transactions across the communication channel, decreasing latency and communication channel usage. However, this requires a local copy of all registers, which can be a significant memory usage. In additional, if a register is accessed by multiple processes or multiple processors, multiple copies of the register may be required, resulting in coherency problems similar to cache coherency problems among various copies.